1. Field of the Invention
The present invention relates to an analog multiplier for multiplying two input signals and more particularly, to an analog multiplier using two triple-tail cells, which is suitable for a Large-Scale Integrated circuit (LSI) and capable of completely linear operation.
2. Description of the Prior Art
A conventional four-quadrant analog multiplier of this type is shown in FIG. 1, which has a Complementary MOS (CMOS) structure. This multiplier is disclosed in a paper, IEE Electronics Letters, Vol. 28, No. 7, pp. 649-650, March 1992, entitled "Four-Quadrant CMOS ANALOGUE MULTIPLIER", written by Y. H. Kim and S. B. Park.
This paper includes some mistakes in its circuit diagram. The circuit configuration shown in FIG. 1 is a corrected one by the inventor, Kimura. The operation principle of this conventional multiplier explained below was given through the inventor's analysis.
In FIG. 1, this multiplier includes a first triple-tail cell of n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) M101, M102, and M105 whose sources are coupled together and a second triple-tail cell of n-channel MOSFETs M103, M104, and M106 whose sources are coupled together.
The coupled sources of the MOSFETs M101, M102, and M105 of the first triple-tail cell are connected to one terminal of a constant current sink 103 sinking a constant current I.sub.B. The other terminal of the constant current sink 103 is applied with a power supply voltage V.sub.ss. The first triple-tail cell is driven by the constant current (i.e., tail current) I.sub.B.
The coupled sources of the MOSFETs M103, M104, and M106 of the second triple-tail cell are connected to one terminal of a constant current sink 104 sinking a same constant current I.sub.B as the constant current sink 103. The other terminal of the constant current sink 103 is applied with the power supply voltage V.sub.ss. The second triple-tail cell is driven by the same constant current (i.e., tail current) I.sub.B as the first triple-tail cell.
Gates of the MOSFETs M101, M102, and M105 of the first triple-tail cell are applied with input voltages (V.sub.x /2), (-V.sub.x /2), and (-V.sub.y /2), respectively. Gates of the MOSFETs M103, M104, and M106 of the second triple-tail cell are applied with input voltages (-V.sub.x /2), (-V.sub.x /2), and (V.sub.y /2), respectively.
Drains of the MOSFETs M101 and M103 are coupled together to be connected to an input terminal of a current mirror circuit 105. An output terminal of the current mirror circuit 105 is connected to an input terminal of a current mirror circuit 107. A drain of the MOSFET M105 is connected to a constant current source 101 supplying a constant current I.sub.B1.
Drains of the MOSFETs M102 and M104 are coupled together to be connected to an input terminal of a current mirror circuit 106. An output terminal of the current mirror circuit 106 is connected to an output terminal of the current mirror circuit 107. A drain of the MOSFET M106 is connected to a constant current source 102 supplying a same constant current IaI as the constant current source 101.
A p-channel MOSFET M107 is further provided to the first triple-tail cell. A drain of the MOSFET M107 is connected to the coupled sources of the M101, M102, and M105 of the first triple-tail cell. A gate of the MOSFET M107 is connected to the drain of the MOSFET M105. A source of the MOSFET M107 is applied with a power supply voltage V.sub.DD.
A p-channel MOSFET M108 is further provided to the second triple-tail cell. A drain of the MOSFET M108 is connected to the coupled sources of the M103, M104, and M106 of the second triple-tail cell. A gate of the MOSFET M108 is connected to the drain of the MOSFET M106. A source of the MOSFET M108 is applied with the power supply voltage V.sub.DD.
Next, the operation principle of the conventional multiplier shown in FIG. 1 is explained below.
It is supposed that the MOSFETs M101 to M108 are matched in characteristics and that the channel-length modulation and the body effect can be ignored. Then, if a drain current I.sub.D of each MOSFET varies with its gate-to-source voltage V.sub.GS according to the square-law characteristic, the drain current I.sub.D is typically expressed by the following equation (1). EQU I.sub.D =.beta.(V.sub.GS -V.sub.TH).sup.2 ( 1)
In the equation (1), V.sub.TH is the threshold voltage of the MOSFET and .beta. is the transconductance parameter thereof. The transconductance parameter .beta. is defined as ##EQU1## where .mu. is the mobility of a carrier, C.sub.OX is the gate-oxide capacitance per unit area, and W and L are a gate width and a gate length of each MOSFET, respectively.
Here, drain currents of the MOSFETs M101, M102, M103, M104, M105, M106, M107, and M108 are expressed as I.sub.D1, I.sub.D2, I.sub.D3, I.sub.D4, I.sub.D5, I.sub.D6, I.sub.D7, and I.sub.D8, respectively. Since the drain current I.sub.D7 flows into the constant current sink 103 through the coupled sources of the MOSFETs M101, M102, and M105, the sum of the drain currents I.sub.D1, I.sub.D2, I.sub.D5, and I.sub.D7 is equal to the constant tail current I.sub.B of the constant current sink 103. Therefore, the following equation (2) is established. EQU I.sub.B =I.sub.D1 +I.sub.D2 +I.sub.D5 +I.sub.D7 ( 2)
The gate of the MOSFET M107 is connected to the drain of the MOSFET M105 and therefore, the drain current I.sub.D7 of the MOSFET M107 is controlled by the drain voltage of the MOSFET M105.
The MOSFET M105 is driven by the constant current I.sub.B1 supplied by the constant current source 101, in other words, the drain current I.sub.D5 of the MOSFET M105 is kept at I.sub.B1 (i.e., I.sub.D5 =I.sub.B1). Therefore, a gate-to-source voltage V.sub.GS5 of the MOSFET M105 needs to be kept constant. This means that a source voltage V.sub.ss of the MOSFET M105, which is equal to source voltages of the MOSFETs M101 and M102, needs to vary according to an applied gate voltage V.sub.G5 of the MOSFET M105 to provide the constant gate-to-source voltage V.sub.GS5.
Since the input voltage (-V.sub.y /2) is applied to the gate of the MOSFET M105, the gate voltage V.sub.G5 of the MOSFET M105 is given as V.sub.R -(1/2)V.sub.y !, where V.sub.R is a specific reference voltage. Therefore, the gate-to-source voltage V.sub.GS5 of the MOSFET M105 is given as EQU V.sub.GS5 =V.sub.G5 -V.sub.S5 =V.sub.R -(1/2)V.sub.y -V.sub.S5.
Accordingly, the drain current I.sub.D5 of the MOSFET M105 is expressed as the following equation (3) using the above equation (1). EQU I.sub.D5 =.beta.(V.sub.GS5 -V.sub.TH).sup.2 =.beta.(V.sub.R 1/2V.sub.y -V.sub.S5 -V.sub.TH).sup.2 =I.sub.B1 ( 3)
From the equation (3), the common source voltage V.sub.S5 of the MOSFETs M1, M2, and M5 is given by the following expression (4). ##EQU2##
It is seen from the expression (4) that the MOSFET M105 serves to shift or vary the common source voltage V.sub.S5 according to the applied input voltage (-V.sub.y /2), thereby keeping the gate-to-source voltage V.sub.GS5 of the MOSFET M105 constant.
Similarly, the gate voltages V.sub.G1 and V.sub.G2 of the MOSFETs M101 and M102 are given as V.sub.R -(1/2)V.sub.x ! and V.sub.R +(1/2)V.sub.x !, respectively. Therefore, the gate-to-source voltages V.sub.GS1 and V.sub.GS2 of the MOSFETs M101 and M102 are given as EQU V.sub.GS1 =V.sub.G1 -V.sub.S1 =V.sub.R -(1/2)V.sub.x -V.sub.S5, and EQU V.sub.GS2 =V.sub.G2 -V.sub.S2 =V.sub.R +(1/2)V.sub.x -V.sub.S5.
Accordingly, using the above equation (4), the drain currents I.sub.D1 and I.sub.D2 of the MOSFETs M101 and M102 are given by the following equations (5) and (6), respectively. ##EQU3##
As a result, from these equations (5) and (6), the differential output current (I.sub.D2 -I.sub.D2) of the MOSFETs M101 and M102 is expressed by the following equation (7). ##EQU4##
Similarly, since the drain current I.sub.D8 flows into the constant current sink 104 through the coupled sources of the MOSFETs M103, M104, and M106, the sum of the drain currents I.sub.D3, I.sub.D4, I.sub.D6, and I.sub.D8 is equal to the constant tail current I.sub.B of the constant current sink 104. Therefore, the following equation (8) is established. EQU I.sub.B =I.sub.D3 +I.sub.D4 +I.sub.D6 +I.sub.D8 ( 8)
The gate of the MOSFET M108 is connected to the drain of the MOSFET M106 and therefore, the drain current I.sub.D8 of the MOSFET M10B is controlled by the drain voltage of the MOSFET M106.
The MOSFET M106 is driven by the constant current I.sub.B1 supplied by the constant current source 102, in other words, the drain current I.sub.D6 of the MOSFET M106 is kept at I.sub.B1 (i.e., I.sub.D6 I.sub.B1). Therefore, a gate-to-source voltage V.sub.GS6 of the MOSFET M106 needs to be kept constant. This means that a source voltage V.sub.S6 of the MOSFET M106, which is equal to source voltages of the MOSFETs M103 and M104, needs to vary according to an applied gate voltage V.sub.G6 of the MOSFET M106 to provide the constant gate-to-source voltage V.sub.GS6.
Since the input voltage (V.sub.y /2) is applied to the gate of the MOSFET M106, the gate voltage V.sub.G6 of the MOSFET M106 is given as V.sub.R +(1/2)V.sub.y !. Therefore, the gate-to-source voltage V.sub.GS6 of the MOSFET M106 is given as EQU V.sub.GS6 =V.sub.G6 -V.sub.S6 =V.sub.R +(1/2)V.sub.y -V.sub.S6.
Accordingly, the drain current I.sub.D6 of the MOSFET M106 is expressed as the following equation (9) using the above equation (1). EQU I.sub.D6 =.beta.(V.sub.GS6 -V.sub.TH).sup.2 =.beta.(V.sub.R +1/2V.sub.y -V.sub.S6 -V.sub.TH).sup.2 =I.sub.B1 ( 9)
From the equation (9), the common source voltage V.sub.S6 of the MOSFETs M3, M4, and M6 is given by the following expression (10). ##EQU5##
It is seen from the expression (10) that the MOSFET M106 serves to shift or vary the common source voltage Vsg according to the applied input voltage (V.sub.y /2), thereby keeping the gate-to-source voltage V.sub.GS6 of the MOSFET M106 constant.
Similarly, the gate voltages V.sub.G3 and V.sub.G4 of the MOSFETs M103 and M103 are given as V.sub.R +(1/2)V.sub.x ! and V.sub.R -(1/2)V.sub.x !, respectively. Therefore, the gate-to-source voltages V.sub.GS33 and V.sub.GS4 of the MOSFETs M103 and M104 are given as EQU V.sub.GS3 =V.sub.G3 -V.sub.S3 =V.sub.R +(1/2)V.sub.x -V.sub.S6, and EQU V.sub.GS4 =V.sub.G4 -V.sub.S4 =V.sub.R -(1/2)V.sub.x -V.sub.S6.
Accordingly, using the above equation (10), the drain currents I.sub.D3 and I.sub.D4 of the MOSFETs M103 and M104 are given by the following equations (11) and (12), respectively. ##EQU6##
As a result, from these equations (11) and (12), the differential current of the MOSFETs M103 and M104 is expressed by the following equation (13). ##EQU7##
The drains of the MOSFETs M101 and M103 are commonly connected to the input terminal of the current mirror circuit 105. Therefore, an input current i9 of the current mirror circuit 105 is expressed by the sum of the drain currents I.sub.D1 and I.sub.D3 ; i.e., i.sub.9 =I.sub.D1 +I.sub.D3.
A mirror current i.sub.10 of the current i.sub.9, which is equal to i.sub.9, is outputted by the current mirror circuit 105 and then, is inputted into the input terminal of the current mirror circuit 107. A mirror current i13, which is equal to i.sub.9, is outputted by the current mirror circuit 107.
Similarly, the drains of the MOSFETs M102 and M104 are commonly connected to the input terminal of the current mirror circuit 106. Therefore, an input current i.sub.11 of the current mirror circuit 106 is expressed by the sum of the drain currents I.sub.D2 and I.sub.D4 ; i.e., i.sub.11 =I.sub.D2 +I.sub.D4.
A mirror current i.sub.12 of the current i.sub.11, which is equal to i.sub.11, is outputted by the current mirror circuit 106 and then, is inputted into the output terminal of the current mirror circuit 107.
As a result, a differential output current i.sub.out of the conventional multiplier shown in FIG. 1 is expressed as the following expression (14). ##EQU8##
It is seen from the above expression (14) that the differential output current i.sub.out is proportional to the product V.sub.x .multidot.V.sub.y of the first and second differential input voltages V.sub.x and V.sub.y, which realizes a four-quadrant multiplier operation.
Although the conventional CMOS multiplier shown in FIG. 1 realizes a complete linear operation, there is a problem that the frequency characteristic degrades. This is because the p-channel MOSFETs M107 and M108, which are inferior in frequency characteristic to n-channel MOSFETS, are used in the signal paths.
Also, the drain currents I.sub.D7 and I.sub.D8 of the MOSFETs M107 and M108, which do not appear in the differential output current i.sub.out, need to flow into the first and second triple-tail cells, respectively. The drain currents I.sub.D7 and I.sub.D8 are typically set as comparatively large. Consequently, there is another problem that a circuit current increases.
Further, to raise the maximum operable input voltages, a larger current needs to be supplied to this conventional multiplier. Specifically, if the input voltage V.sub.y becomes high, the source voltages V.sub.S5 and V.sub.S6 need to be raised according to the input voltage V.sub.y. In this case, the drain currents I.sub.D7 and I.sub.D8 of the MOSFETs M107 and M108 will be necessarily large. This leads to further circuit-current increase.
An analog multiplier is an essential function block in the analog signal applications.
Also, the need of a CMOS analog multiplier has been becoming stronger and stronger in recent years.